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Features
* * * * * * * *
Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components PSSO20 Plastic Package with Down-set Paddle Heat Slug or HP-VFQFP-N20 with Extended Performance and Flipchip Version
BluetoothTM/ISM 2.4-GHz FrontEnd IC T7024
Electrostatic sensitive device. Observe precautions for handling.
Description
The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like BluetoothTM, DECT, and many other ISM applications according to FCC part 15. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram
RX_ON LNA_OUT V1_PA V2_PA V2_PA PA_IN RAMP
Preliminary
TX/RX/ standby control
TX
GND
PU
GND
LNA
PA
SiGe Front End
T7024
R_SWITCH GND GND V3_PA_OUT SWITCH_OUT V3_PA_OUT V3_PA_OUT VS_LNA LNA_IN GND
Rev. 4533A-BLURF-09/02
1
Pin Configuration
Figure 2. Pinning PSSO20
R_SWITCH 1 20 PU
Figure 3. Pinning HP-VFQFP-N20
GND 3 LNA_IN 4 VS_LNA 5 GND 6 V3_PA_OUT 7 T7024
18 LNA_OUT 17 GND 16 PA_IN 15 V1_PA 14 GND 13 V2_PA 12 V2_PA 11 RAMP
10
GND VS_LNA GND LNA_IN GND
9 8 7 6 5 4
SWITCH_OUT 2
19 RX_ON
V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP
11 12 13 14 15 16 17 18 19 20
T7024
3 2 1
SWITCH_OUT R_SWITCH PU RX_ON LNA_OUT
V3_PA_OUT 8 V3_PA_OUT 9
GND 10
Pin Description
Pins PSSO20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Slug Pins N20 4 5 6 7 9 8 11 12 13 10 15 16 17 14 19 20 18 1 2 3 Slug Symbol R_SWITCH SWITCH_OUT GND LNA_IN VS_LNA GND V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP V2_PA V2_PA GND V1_PA PA_IN gnd LNA_OUT RX_ON PU GND Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Supply voltage input for low-noise amplifier Ground Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Ground Power ramping control input Inductor to power supply for power amplifier Inductor to power supply for power amplifier Ground Supply voltage for power amplifier Power amplifier input Ground Low-noise amplifier output RX active high Power-up active high Ground
2
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V2_PA V2_PA GND V1_PA PA_IN
T7024
Figure 4. Pad Location, Thickness: 450 m
3180 m
19 LNA_OUT
18 GND
17 PA_IN
16 V1_PA
15 GND
14 GND
13 V2_PA 12
1600 m
20 RX_ON
21 PU
RAMP
11 1 2
R_SWITCH SWITCH_OUT 3 GND
Pad diameter 180 m Ball diameter 200 m
GND
10 4 LNA_IN 5 GND 6 VS_LNA 7 GND 8 GND 9 V3_PA_OUT GND
Pad Description
Pad 1 2 3 4 5 6 7 8 9 Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Ground Supply voltage input for low-noise amplifier Ground Ground Inductor to power supply and matching network for power amplifier output GND Ground GND Ground RAMP Power ramping control input V2_PA Inductor to power supply for power amplifier GND Ground GND Ground V1_PA Supply voltage for power amplifier PA_IN Power amplifier input GND Ground LNA_OUT Low-noise amplifier output RX_ON RX active high PU Power-up active high 1. Relative to center of Pad 3. Symbol R_SWITCH SWITCH_OUT GND LNA_IN GND VS_LNA GND GND V3_PA_OUT X-Coordinate of Pad (1) (m) 0 400 0 400 800 1200 1600 2000 2400 Y-Coordinate of Pad (1) (m) 400 400 0 0 0 0 0 0 0
10 11 12 13 14 15 16 17 18 19 20 21 Note:
2780 2780 2780 2450 2050 1650 1250 850 400 0 0 400
150 550 950 1200 1200 1200 1200 1200 1200 1200 800 800
3
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Absolute Maximum Ratings
Parameters Symbol Value Unit
Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT Junction temperature Storage temperature RF input power LNA RF input power PA
VS Tj Tstg PinLNA PinPA
6 150 -40 to +125 5 10
V C C dBm dBm
Thermal Resistance
Parameters Symbol Value Unit
Junction ambient PSSOP20, slug soldered on PCB Junction ambient HP-VFQFP-N20, slug soldered on PCB
RthJA RthJA
19 27
K/W K/W
Operating Range
All voltages are referred to ground (Pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode.
Parameters Symbol Min. Typ. Max. Unit
Supply voltage Supply voltage Supply current TX RX Standby current Ambient temperature
Pins V1_PA, V2_PA and V3_PA_OUT Pin VS_LNA PSSO20 N20 PU = 0
VS VS IS IS IS IS_standby Tamb
2.7 2.7
3.0 3.0 190 165 8 10
4.6 5.5
V V mA mA mA A
-25
+25
+70
C
4
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T7024
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25C
Parameters Power Amplifier
(1)
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Supply voltage Supply current
Pins V1_PA, V2_PA, V3_PA_OUT TX PSSO20 N20
VS IS_TX IS_TX IS_RX IS_standby f
DGp
2.7
3.0 190 165
4.6
V mA mA
RX (PA off), VRAMP 0.1 V Standby current Frequency range Gain-control range Power gain maximum Power gain minimum Ramping voltage maximum Ramping voltage minimum Ramping current maximum Power-added efficiency Saturated output power Input matching (2) Output matching (2) Harmonics at P 1dBCP Standby TX TX TX, Pin PA_IN to V3_PA_OUT TX, Pin PA_IN to V3_PA_OUT TX, power gain (maximum) Pin RAMP TX, power gain (minimum) Pin RAMP TX, VRAMP = 1.75 V, Pin RAMP TX PSSO20 N20 TX, input power = 0 dBm referred to Pins V3_PA_OUT TX, Pin PA_IN TX, Pins V3_PA_OUT TX, Pins V3_PA_OUT TX, Pins V3_PA_OUT Switch-out current output Standby, Pin SWITCH_OUT RX TX at 100 W TX at 1.2 kW TX at 33 kW TX at
Low-noise Amplifier
(3)
10 10 2.4 60 28 -40 1.7 1.75 0.1 0.5 30 35 22.0 35 40 23 <1.5:1 <1.5:1 -30 -30 1 1 1.7 7 17 19 2.7 3.0 8 5.5 9 0.5 24.0 42 30 33 -17 1.83 2.5
A A GHz dB dB dB V V mA % % dBm
Gp Gp VRAMP max VRAMP min IRAMP max PAE PAE Psat Load VSWR Load VSWR 2 fo 3 fo IS_O_standby IS_O_RX IS_O_100 IS_O_1k2 IS_O_33k IS_O_R VS IS IS
dBc dBc A A mA mA mA mA V mA mA
T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND)
Supply voltage Supply current Supply current (LNA and control logic) Notes:
All, Pin VS_LNA RX TX (control logic active) Pin VS_LNA
1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZC = 50 W. 2. With external matching network, load impedance 50 W. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components.
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25C
Parameters Test Conditions
Symbol Min. Typ. Max. Unit
Standby current Frequency range Power gain Noise figure Gain compression 3rd-order input interception point Input matching
(4) (4)
Standby, Pin VS_LNA RX RX, Pin LNA_IN to LNA_OUT RX, PSSO20 N20
IS_standby f Gp NF NF O1dB IIP3 VSWRin VSWRout ViH ViL IiH IiL 2.4 0 -9 -16 2.4 15
1 16 2.5 2.1 -7 -14
10 2.5 19 2.8 2.3 -6 -13 2:1 2:1 VS, LNA 0.5
A GHz dB dB dBm dBm
RX, referred to Pin LNA_OUT RX RX, Pin LNA_IN RX Pin LNA_OUT = `1' Pins RX_ON and PU = `0' = `1' ViH = 2.4 V = `0'
Output matching High input level Low input level
Logic input levels (RX_ON, PU)
V V A A
High input current Low input current Notes:
40
60 0.2
1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZC = 50 W. 2. With external matching network, load impedance 50 W. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components.
Control Logic for LNA and T/R Switch Driver
Operation Mode PU RX_ON
Standby TX RX
0 1 1
0 0 1
6
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T7024
Typical Operating Characteristics
Figure 5. LNA (PSSO20): Gain and Noise Figure versus Frequency
20 8 7
Gain
15
6 5
Gain (dB)
10
4 3
5
2 1
0 2000
2200
2400
2600
2800
0 3000
Frequency (MHz)
Figure 6. LNA (N20): Gain and Noise Figure versus Frequency
25 5
20
Gain
4
15
3
Gain (dB)
10
2
5
1
0 2000
2200
2400
2600
2800
0 3000
Frequency (MHz)
Figure 7. LNA: NF and Gain versus Temperature
2.5 2.0
NF
1.5
VS = 3 V
Relative gain, relative NF (dB)
1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -40
Gain
-20
0
20
40
60
80
Temperature (C)
NF (dB)
NF
NF (dB)
NF
7
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Figure 8. LNA: Typical Switch-out Current versus Rswitch
20
16
IS_O (mA)
12
8
4
0 1 10 100 1000 10000 100000 1000000 10000000
Rswitch (W)
Figure 9. PA (PSSO20): Output Power and PAE versus Supply
50
I_S_TX
250
40
PAE
220
Pout (dBm), PAE (%)
30
190
20
Pout f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm
160
10
130
0 2.7 3.1 3.5 3.9 4.3
100 4.7
Supply Voltage (MHz)
Figure 10. PA (PSSO20): Output Power and PAE versus Ramp Voltage
50
PAE
250
30
200
Pout
Pout (dBm), PAE (%)
10
150
-10
I_S_TX f = 2.4 GHz VS = 3 V PinPA = 0 dBm
100
-30
50
-50 1.2 1.4 1.6 1.8 2.0
0
Vramp (V)
8
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I_S_TX (mA)
I_S_TX (mA)
T7024
Figure 11. PA (PSSO20): Output Power and PAE versus Input Power
40
PAE Gain
250
Pout (dBm), PAE (%), Gp (dB)
30
200
20
I_S_TX
150
10
VS = 3 V f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm Pout
100
0
50
-10 -40
0 -30 -20 -10 0 10
Input Power (dBm)
Figure 12. PA (PSSO20): Output Power and PAE versus Frequency
50
I_S_TX
250
40
200
Pout (dBm), PAE (%)
30
150
20
Pout VS = 3 V Vramp = 1.7 V PinPA = 0 dBm
100
10
50
0 2400
2420
2440
2460
2480
0 2500
Frequency (MHz)
Figure 13. PA (N20): Output Power and PAE versus Supply Voltage
50 250
40
PAE I_S_TX
220
Pout (dBm), PAE (%)
I_S_TX (mA)
190 160 130 100
PAE
30
20
f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm
Pout
10
0 2.7 3.1 3.5 3.9 4.3 4.7
Supply Voltage (MHz)
I_S_TX (mA)
9
4533A-BLURF-09/02
Figure 14. PA (N20) Output Power and PAE versus Ramp Voltage
50
PAE
250
30
Pout
200
Pout (dBm), PAE (%)
10
150
-10
I_S_TX f = 2.4 GHz VS = 3 V PinPA = 0 dBm
100
-30
50
-50 1.2 1.4 1.6 1.8 2.0
0
Vramp (V)
Figure 15. PA (N20): Output Power and PAE versus Input Power
50 300
Pout (dBm), PAE (%), Gp (dB)
40
Gain
PAE
250
20
I_S_TX
150
10
VS = 3 V f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm Pout
100
0
50
-10 -40
0 -30 -20 -10 0 10
Input Power (dBm)
Figure 16. PA (N20): Output Power and PAE versus Frequency
50
PAE
250
40
200
Pout (dBm), PAE (%)
30
I_S_TX
150
20
Pout VS = 3 V Vramp = 1.8 V PinPA = 0 dBm
100
10
50
0 2400
2420
2440
2460
2480
0 2500
Frequency (MHz)
10
T7024
4533A-BLURF-09/02
I_S_TX (mA)
I_S_TX (mA)
30
200
I_S_TX (mA)
T7024
Figure 17. LNA: Supply Current versus Temperature
8.0 7.8 7.6
Supply current (V)
7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80
Temperature (C)
Figure 18. PA (PSSO20): Current versus Vramp and Temperature
200 180 160
-40C
140 120
I ( dBm )
100
0C
40C
80 60 40
80C
20 0 0.1 1.0 10.0 100.0 1000.0
Vramp current ( A )
Figure 19. PA (PSSO20, N20): Pout versus Vramp and Temperature
30
f = 2.4 GHz VS = 3 V Pin = 0 dBm
20
5
Pout ( dBm )
10
0
80
25 -15
-10
-40C
-20 1.0 1.2 1.4 1.6 1.8
Vramp ( V )
11
4533A-BLURF-09/02
Input/Output Circuits
Figure 20. Input Circuit PA_IN/V1_PA
V1_PA
PA_IN
GND
Figure 21. Input Circuit RAMP/V1_PA
V1_PA
RAMP
Figure 22. Input Circuit V2_PA
V2_PA
GND
12
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T7024
Figure 23. Input/Output Circuit V3_PA_OUT
V3_PA_OUT
GND
Figure 24. Input Circuit SWITCH_OUT/R_SWITCH
V1_PA
SWITCH_OUT
R_SWITCH GND
Figure 25. Input Circuit LNA_IN/VS_LNA
VS_LNA
LNA_IN
GND
13
4533A-BLURF-09/02
Figure 26. Input Circuit PU/RX_ON
VS_LNA
LNA_IN / PU
Figure 27. Output Circuit LNA_OUT
VS_LNA
LNA_OUT
GND
14
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T7024
Figure 28. Application Board PSSO20
LNA OUT RX ON 100p PA IN 10p 3.9nH 5.6nH 3.9p PU 100p 3p3 HQ 15p 1n 1u PA ramp 56p
20 19 18 17 16 15 14 13 12 11
1n 1u
V1_PA
V2_PA
T7024
1 2 3 4 5 6 7 8 9 10
harm. termination 1p5 HQ R1 is selected with DIL-switch 56p 1.8p R1 Var 1u 0p8 HQ 15nH 10p 1n 1u Switch Out LNA IN VS_LNA V3_PA PA OUT
pin-diode replaced by LED on applicationboard
Blocking capacitors depending on application
Figure 29. Layout for PSSO20
LNA_OUT PA_IN
LNA_SUPPLY 100pF 100pF 3.9nH 3.9pF 0R 5.6nH 15pF 3.3pF HQ 56pF 15nH 56pF 0R DIL-Switch 2k7 0R 390R 1.8pF LED 0R
1nF 1uF 1nF 1uF
PA_SUPPLY
1nF 10pF 1uF
1uF 1.5pF HQ
0.8pF HQ
0R
LNA_IN
PA_OUT
15
4533A-BLURF-09/02
Gerberfiles are available on request. The application board consists of 4 layers: 1. top layer: RF-signals, 35 m Cu 2. spacing: 490 m FR4 3. second layer: GND, 35 m Cu 4. spacing: 550 m FR4 5. third layer: GND (optional), 35 m Cu 6. spacing: 490 m FR4 7. bottom layer: DC connection, 35 m Cu
Figure 30. Application Board N20
LNA OUT PA IN 15p 1n 1u V1_PA
2.2p 1p RX ON 100p PU 100p
20 19 18 17 16 1 15 14 2 3 4 5
15p 1n 1u 3p3
V2_PA
PA ramp harm. termination 56p
T7024
67 8
13
12 11 9 10
2p2 R1 is selected with DIL-switch R1 Var pin-diode replaced by LED on applicationboard Switch Out 56p 1.8p 18nH 1u 10p 1n 1u Blocking capacitors depending on application 0p8
LNA IN
VS_LNA
V3_PA
PA OUT
16
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T7024
Figure 31. Layout for N20
LNA_OUT PA_IN
0R 0R 2.2pF 100pF 100pF 0.8pF HQ
0R
1nF 15pF 1 mF 0R 15pF1nF 0R 1pF 1 mF 3.3pFHQ 56pF 18nH HQ
0R 56p 1.8pF LED 0R 2k7 390R LNA_IN 0R
1 mF
2.2pF HQ
1 mF
10pF1nF
PA_OUT
Gerberfiles are available on request. The application board consists of 4 layers: 1. top layer: RF-signals, 35 m Cu 2. spacing: 490 m FR4 3. second layer: GND, 35 m Cu 4. spacing: 550 m FR4 5. third layer: GND (optional), 35 m Cu 6. spacing: 490 m FR4 7. bottom layer: DC connection, 35 m Cu
17
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Ordering Information
Extended Type Number Package Remarks
T7024-TRS T7024-TRQ T7024-PGS T7024-PGQ T7024-DB
PSSO20 PSSO20 HP-VFQFP-N20 HP-VFQFP-N20 Flipchip
Tube Taped and reeled Tube Taped and reeled -
Package Information
18
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T7024
19
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4533A-BLURF-09/02 xM

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